This invention relates generally to mass digital data storage systems using flash electrically erasable and programmable read only memory (xe2x80x9cEEPROMxe2x80x9d) technology, and, more specifically, to techniques of controlling the use of such systems in order to improve their useful life.
An advantage of using EEPROM technology is that a solid-state, non-volatile memory is provided, which can be repetitively reprogrammed. Each EEPROM cell includes an electrically floating gate positioned over a substrate channel between source and drain regions. A thin gate oxide layer separates the floating gate from the substrate. The threshold level of the cell is controlled by an amount of charge that is placed on the floating gate. If the charge level is above some threshold, the cell is read to have one state, and if below that threshold, is read to have another state.
The desired floating gate charge level is programmed by applying an appropriate combination of voltages to the source, drain, substrate and a separate control gate, for a designated period of time, in order to cause electrons to move from the substrate to the floating gate through the gate oxide layer. Current leakage from the floating gate is very small over time, thereby providing permanent storage. The charge,level on the floating gate can be reduced by an appropriate combination of voltages applied to the elements described above, but it is preferable to include a separate erase gate that is positioned adjacent the floating gate with a thin layer of tunnel oxide between them.
A large number of such cells form a memory. The cells are preferably arranged on a semiconductor integrated circuit chip in a two-dimensional array with a common control gate provided for a row of such cells as a word line and the cells in each column having either their drain or source connected to a common bit line. Each cell is then individually addressable by applying the appropriate voltages to the word and bit lines that intersect at the desired cell. Rather than providing for such individual addressing for the purpose of erasing the cells, however, the erase gates of a block of cells are generally connected together in order to allow all of the cells in the block to be erased at the same time, i.e., in a xe2x80x9cflashxe2x80x9d.
In operating such a memory system, cells can be rewritten with data by either programming with electrons from the substrate or erasing through their erase gates, depending upon the state in which they are found and the state to which they are to be rewritten. However, flash EEPROM systems are generally operated by first erasing all of the cells in a erasable block to a common level, and then reprogramming them to desired new states.
Flash EEPROM mass storage systems have many advantages for a large number of applications. These advantages include their non-volatility, speed, ease of erasure and reprogramming, small physical size and similar factors. Because there are no mechanical moving parts, such systems are not subject to failures of the type most often encountered with hard and floppy disk mass storage systems. However, EEPROM cells do have a limited lifetime in terms of the number of times they can be reprogrammed or erased. As the number of cycles to which a cell is subjected reaches a few tens of thousands, it begins to take more voltage and/or time to both program and erase the cell. This is believed due to electrons being trapped in the respective gate and tunnel dielectric layers during repetitive programming and erase cycles. After a certain number of cycles, the number of electrons that are so trapped begin to change the operating characteristics of the cell. At some point, after one hundred thousand or more such cycles, so much voltage or time is required to either program or erase the cell, or both, that it becomes impractical to use it any further. The lifetime of the cell has at that point ended. This characteristic of EEPROM cells is described in European Patent Application Publication No. 349,775xe2x80x94Harari (1990).
Therefore, it is a principal object of the present invention, given a finite lifetime of individual EEPROM cells, to maximize the service lifetime of an entire mass storage EEPROM system.
This and additional objects are accomplished by the present invention, wherein, briefly and generally, the EEPROM array of cells is divided into two or more interchangeable banks of cells, each bank having one or more blocks of cells. A block is the smallest group of cells that is erasable or programmable at one time. A memory controller provides for interchanging such banks over the lifetime of the memory at times when it is detected that they are receiving significantly uneven use.
If such an interchange, or wear leveling, is not carried out in the case where there is significantly uneven use among groups of EEPROM cells, one group will reach its end of lifetime while other groups have significant life left in them. When one group reaches an end of lifetime, the entire memory may have to be replaced unless extra groups of memory cells are included in the system for replacing those that reach their lifetime. However, the techniques of the present invention allow for extending overall memory system lifetime without having to provide such replacement groups of memory cells. The ability to interchange groups of cells to result in more even wear among the groups is particularly advantageous in computer system applications wherein flash EEPROM memory is used in the nature of a disk drive. This is because the memory is subjected to frequent erase and reprogramming cycles in some groups but not others, and since the large capacity of the memory would require a large number of spare groups in order to obtain a reasonable memory system lifetime without use of the group interchange technique of the present invention.
Additional objects, advantages and features of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.